Advanced nonvolatile memory devices typically include a control gate electrode and an underlying floating gate electrode, which retains an electrical charge. The cell size of such a nonvolatile memory device can be large, because a number of components are necessary to form the memory array. In order to fabricate a nonvolatile memory array having a minimal surface area, the control gate electrode and the floating gate electrode can be formed by a self-aligned etch process.
FIG. 1 illustrates, in plan view, a composite masking diagram of several layers in a portion of an erasable-read-only-memory (EPROM) array arranged in accordance with the prior art. FIGS. 2-1 through 2-4 illustrate, in cross-section, process steps in accordance with the prior art for the fabrication of the EPROM device using a self-aligned etch process. The cross-sections are taken through the section line 2--2 illustrated in FIG. 1.
FIG. 2-1 illustrates, in cross-section, a portion of a semiconductor substrate 10 at a processing stage immediately prior to the self-aligned etch step. Substrate 10 is separated, at the surface, into a plurality of active device regions by a thick field oxide 12. A thin-gate oxide layer 14 overlies the surface of substrate 10 in the active device regions. Overlying the gate oxide and the field oxide is a first layer 16 of polycrystalline silicon. This polycrystalline silicon layer is used to form a floating gate electrode of the EPROM device. Overlying polycrystalline silicon layer 16 is an inter-level-dielectric (ILD) 18. The inter-level-dielectric is typically an oxide, nitride, or an oxide-nitride-oxide (ONO) layer. Gate oxide 14 is typically a thermally grown oxide having a thickness of about 10 nanometers. Polycrystalline silicon layer 16 is typically deposited by chemical vapor deposition to a thickness of about 200 nanometers, and ILD 18 is typically a composite dielectric layer having a thickness of about 30.0 nanometers.
As illustrated in FIG. 2-1, polycrystalline silicon layer 16 and ILD 18 are patterned and etched to remove portions of these layers from semiconductor substrate 10. A second polycrystalline silicon layer 20 overlies the patterned portions of layers 16 and 18, and the remaining portions of substrate 10. A photoresist layer 22 overlies second polycrystalline silicon layer 20 to act as an etch mask for a self-aligned etch process.
The self-aligned etch process begins, as illustrated in FIG. 2-2, with the removal of portions of second polycrystalline silicon layer 20 exposed by photoresist layer 22. The first step of the self-aligned etch process forms a control gate 24 and a wordline 26, removes polycrystalline silicon overlying gate oxide layer 14 in regions of substrate 10 adjacent to field oxide 12 and to wordline 26.
The self-aligned etching process continues with the removal of exposed portions of ILD 18, as illustrated in FIG. 2-3. The dielectric etching process also removes gate oxide layer 14 overlying substrate 10 leaving an exposed surface region 28 adjacent to wordline 26. As illustrated in FIG. 1., exposed surface regions 28 reside adjacent to field oxide regions 12 at a location adjacent to wordlines 26. A portion of wordline 26 functions as control gate 24 in regions where wordline 26 crosses over the active regions of substrate 10.
After etching ILD 18, exposed portions of first polycrystalline silicon layer 16 are removed, as illustrated in FIG. 2-4. The etching process forms a floating gate electrode 30 separated from control gate 24 by ILD 18. Upon completion of the self-aligned etching process, a drain region 32 is formed in substrate 10 on either side of floating gate electrode 30.
In the self-aligned etch process, the monocrystalline silicon substrate in exposed surface region 28 is unavoidably exposed to the same etchant used to pattern first polycrystalline silicon layer 16. During the step in the self-aligned etching process that forms floating gate 30, exposed surface region 28 is subjected to the etchants used to remove first polycrystalline silicon layer 16. Because semiconductor substrate 10 is typically a monocrystalline silicon material, the etching process used to form floating gate 30 also etches silicon in exposed surface region 28. The etching process removes silicon in exposed surface region 28 to a varying extent depending upon the etching characteristics of the polycrystalline silicon etch process. The unwanted removal of monocrystalline silicon in exposed surface region 28 pits the silicon surface. Pitting the substrate surface causes the development of high electric field regions in the ground plane, which degrades the performance of the EPROM device.
One technique for avoiding exposure of the substrate surface during the formation of a floating gate, such as floating gate 30, is to use a non-self-aligned etching process. In the non-self-aligned process, floating gate 30 is completely formed prior to the deposition and etching of a second polycrystalline silicon layer. Once deposited, the second polycrystalline silicon layer is patterned and etched to form a control gate electrode which overlies a portion of the substrate surface in addition to the floating gate electrode. While the non-self-aligned process avoids unwanted etching of the substrate surface, this process results in unwanted parasitic capacitance between the control gate electrode, and the substrate surface. The resulting stray capacitance increases bitline and wordline capacitive loading in the EPROM device.